1. Field
The following relates to microelectronic circuits, and more particularly, to single-event effect (“SEE”) resistant or hardened circuits.
2. Related Art
Integrated circuits used in devices that operate in intergalactic space, earth orbital space, and high atmospheric altitudes (e.g., commercial flight altitudes) generally have to be highly reliable and operate using very low levels of power. Along with these necessities, space, weight and cost limitations generally cause these integrated circuits be very densely populated and highly complex.
As a consequence of operating in intergalactic space, earth orbital space, and high atmospheric altitudes, however, the integrated circuits are exposed to a large amount of radiation, which can effect their operation and, in turn, their reliability. Because the Earth's magnetic field deflects most outer space radiation, terrestrial-based integrated circuits are not normally exposed to large amounts of radiation. Recently, however, several radiation-laden atmospheric storms, which emanated from a coronal mass ejection of the sun, expanded into space, penetrated the Earth's magnetic field and disrupted a significant amount of terrestrial-based devices that use integrated circuits.
The disruptions caused by the radiation events are believed to result from Alpha particles (hereinafter “radiation particles”) interacting with the semiconductor materials (e.g., silicon) that make up the integrated circuits. These radiation particles are by-products of the natural decay of elements, and/or radiation (having kinetic energy) protons, neutrons, electrons, and all the natural elements. The radiation particles are abundant in a wide range of energies in intergalactic space, earth orbital space, high atmospheric altitudes (e.g., commercial flight altitudes), and, as noted above, terrestrial space.
When a radiation particle interferes with an integrated circuit, it can slow the circuit's performance and even upset circuit operation. For example, a radiation particle can change the conductance of a metal-oxide-semiconductor (“MOS”) transistor by changing its threshold voltage (Vt). In Very Large Scale Integration (VLSI) circuits, radiation particles can also generate significant transient voltage and current disturbances on internal supply networks (e.g. power and ground nodes).
A radiation particle that passes into and through an integrated-circuit device transfers energy from the particle into the material surrounding the region into which the particle strikes or “hits.” This energy transfer creates undesirable hole-electron pairs in the surrounding region. This event is known as Linear Energy Transfer (LET), which may be expressed in the units of MeV-cm2/mg. For given material densities, the LET can be converted into units of Coulombs/cm along a track that a particle travels once the activation energy for a hole-electron pair is determined. As a result, the particle can only create a finite amount of charge per unit distance over the length of its track.
As its energy and mass increase, the LET of the particle also increases. The LET, however, does not increase unbounded, but rather reaches a maximum value regardless of how much energy the particle possesses. Once the particle achieves the maximum LET, the addition of more energy counter intuitively results in a reduction in the LET.
The charge that a particle creates may be collected in the structure of the semiconductor device. The amount of collected charge can be calculated by multiplying the LET (C/cm) by the distance that the particle travels along the particle track. For example, the amount of charge collected in a continuous lightly-doped-drain (LDD) region of a MOSFET transistor caused by a particle traveling along the LDD region may be calculated by multiplying the LET (C/cm) by the length of such LDD region.
The charge collection along this particle track, however, may be truncated by oxide regions, degenerately doped P+ and N+ source-drain regions, and/or degenerately doped P+ and N+ well connection regions. While a particle can travel significant distances through the silicon material, the charge collected from the particle traveling along a particle track subsides at a given distance of the particle track. This distance limit may be in the range of a few microns.
The number of hole-electron pairs separated along the track length of the radiation particle, however, is finite, so the nodal voltage disturbances may be temporary or have only a transient effect. In addition, the density of the radiation particles striking the integrated circuit is generally small enough that the disturbances caused by the radiation particles are treated as single events in time. Such transient disturbances are known as single-event transient (SET) conditions.
After experiencing a SET condition, transistor nodes typically return to their desired voltage states. Consequently, the SET condition might not be a problem in and of itself. The consequence of having a temporary voltage disturbance on the transistor node, however, may be problematic because the SET condition may be propagated through the larger system. When the SET condition causes an undesirable change in the state of the larger system, it may be referred to as a single-event upset (SEU) condition.
However, for each particle strike, a finite volume exists around a critical node through which a particle must pass to create a SET and/or SEU condition (collectively referred to as Single Event Effect (SEE) conditions). This finite volume may be referred to as the sensitive volume. If the particle strike is outside the sensitive volume, the created charge may not be able to get to the critical node to cause a SEE condition.
The more charge a circuit can accumulate before a SEE condition results, the greater the LET the circuit can tolerate. Increasing this tolerance is known as SET, SEU, and/or SEE condition hardening. The energized particle environment contains a variety of particle types and energies that result in a wide range of LETs. The density of particles versus LET decreases as the LET increases.
Particles that strike transistors do not have a directional dependence; i.e., they can strike from any direction. If the LET that can cause a SEE condition and size of the sensitive volume is known, the probability of a SEE condition can be determined. These probabilities may be referred to as Soft Error Rates (SER) because they are not due to design or manufacturer defects, and because they can be corrected.
FIGS. 1a and 1b are block diagrams illustrating a simplified layout and cross-section of an N-Channel MOSFET 100 experiencing a particle strike. The N-Channel MOSFET 100 may be fabricated using a bulk material technology, such as bulk CMOS. The N-Channel MOSFET includes an N+ source 102, N+ drain 104, and a P+ body tie 106 all of which may be fabricated in a P-well 108; on top of which a polysilicon and oxide gate 110 may formed.
When a particle strikes the N+ drain 104 and travels along one of finite number of perpendicular particle tracks, such as track A, the charge of the particle may be collected over a certain distance of the P-type well 108, such as the distance ‘d’. The amount of charge collected along distance ‘d’ may be greater than the charge that is created by the initial particle strike.
Consider, for example, the N-channel MOSFET 100 in an “OFF” state in which its source 102 and body tie 106 are connected to VSS, and its drain 104 is held at a high state. The high state may be a state sufficient to reverse bias the PN junction between the N+ drain 104 and the P-Well 108. The N+ drain 104 may be held in the high state, for example, by a P-channel MOSFET (not shown) in an “ON” state. In this reversed-biased state, a depletion region 112 is created in the P-well 108 at interface of the PN junction.
When a particle passes through the PN junction along, for example, the particle track A, then the hole-electron pairs along the particle track A may be separated by the voltage difference between the N+ drain 104 and a P-well 108. The resultant electron charge from the separation of the hole-electron pairs may collect along the particle track ‘A’ in the P-well 108 from about the interface of the N+ drain 104 to the maximum collection distance limit. Consequently, a drain-discharge current along the distance ‘d’ of the particle track ‘A’ may be created from the resultant collection of electrons.
The holes generated along distance ‘d’ are repelled back to the P+ body tie 106, and then travel through the P+ body tie 106 connection to VSS. These traveling holes may also produce a current. Since the P+ body tie 106 may be ohmic or resistive, the current created by the holes traveling through the P+ body tie 106 may create a voltage rise from between the P+ body tie 106 to the VSS connection.
If this voltage rise is large enough to forward bias the P-well 108 to N+ source 102 junction under the gate oxide, a parasitic NPN-bipolar-junction transistor (not shown) coupling the N+ drain 104 to the N+ source 102 may switch to an ON state. The current resulting from the traveling holes is then multiplied by the gain of the parasitic NPN-bipolar-junction transistor (BJT), and appears as a discharge current on the N+ drain 104. This discharge current only flows if the parasitic BJT is turned on. Thus, the discharge current may be approximately equal to the charge created by the particle intrusion multiplied by the gain of the parasitic BJT.
As illustrated, a particle traveling along particle tracks ‘B’ and ‘C’ does not traverse the drain depletion region 110. However, the charges created by particles traveling along the B and C particle tracks diffuse to the nearest depletion region, which in this case is the drain-depletion region 110. As the diffusing holes and electrons reach the drain-depletion region 110, the electrons will be collected by the N+ drain 104 and the holes will be repelled back into the P-well 108, again creating the possibility of turning on the parasitic BJT.
FIGS. 2a and 2b are block diagrams illustrating a simplified layout and cross-section of an N-Channel MOSFET 200 experiencing a particle strike. The N-Channel MOSFET 200 may be fabricated using a bulk material technology, such as bulk CMOS. The N-Channel MOSFET 200 shown in FIGS. 2a and 2b is similar to the N-Channel MOSFET 100 shown in FIGS. 1a and 1b except that the N-Channel MOSFET 200 further includes an N-well 208 into which the P-well 108 is formed.
When a particle travels along the particle track A, the portion of the track from which charge is collected is longer than in the N-Channel MOSFET 100 since the particle also crosses the P-well-to-N-well reversed-biased junction 208 under the N-channel MOSFET 200. Because the particle crosses the P-well-to-N-well reverse-biased junction 208, more electrons may be collected by the N+ drain 104, and more holes may be collected by the P-well 108, which increases the current in the P-well 108.
This may increase the voltage at the junction of the P-well 108 and N+ source 102 under the gate oxide. The net result is that the charge that appears at the N+ drain 104 is the combination of the created charge that flows between the N+ drain 104 and P+ body tie 106 plus the created charge times the gain of the parasitic BJT (if turned on) that flows between N+ drain 104 and N+ source 102. Both of these currents increase the probability of a SET, SEU, and/or SEE conditions.
FIGS. 3a and 3b are schematics of a CMOS inverter 302 and a CMOS two-input NAND gate 304, both of which are susceptible to SEE conditions. The inverter 302 may include a P-Channel transistor 302a coupled in series with an N-Channel transistor 302b. An output signal (designated as the “OUT” signal) is provided from an output terminal 302c located at a node at the intersection of the P-Channel transistor 302a and N-Channel transistor 302b. The gates of the P-Channel transistor 302a and the N-Channel transistor 302b are tied to an input signal (designated as “IN signal”). When the IN signal is a low state, then the P-Channel transistor 302a is in an ON state and the N-Channel transistor 302b is in an OFF state, which causes the OUT signal to be in a high state.
If a particle strikes the N-Channel transistor 302b, then the created charge in N-Channel transistor 302b may result in a pull-down current that competes against the pull-up current of P-Channel transistor 302a, which may potentially disturb the high-state OUT signal. For example, when the pull-down current is sufficiently larger than the pull-up current, then the OUT signal may temporarily switch state, i.e., transition a low-state OUT signal. If the inverter 302 is coupled to another logic gate and the OUT signal undesirably switches state, the effect of the errant OUT signal may be further propagated, thereby causing the other logic gate to experience a SET-induced state change. If the pull-down current is large enough to cause the OUT signal to fall to about a VSS level, the OUT signal may remain at about the VSS level until the P-Channel transistor 302a dissipates all of the created charge.
A particle strike on P-Channel transistor 302a, on the other hand, will not disturb the high OUT voltage state because no voltage difference exists within P-Channel transistor 302a to cause charge movement towards the output terminal. Thus, none of the charge created by the particle strike is removed.
If, immediately after the particle strike, the IN signal transitions to a high state, then the P-Channel transistor 302a may transition to an OFF state and the N-Channel transistor 302b may transition to an ON state. The created charge within the P-type transistor 302a may be collected and not dissipated. As such, the collected charge may hinder or slow down the ability of the N-Channel transistor 302b to pull the OUT signal to a low state. The N-Channel transistor 302b may not be able to pull the OUT signal to the low state until it removes the created charge. In this case, the particle strike may not create an immediate state change, but it can delay a desired state change from occurring.
In addition to causing undesirable state changes, the created hole-electron concentrations can be quite high, e.g., much higher than the surrounding structure of the semiconductor device, i.e., higher than the N or P-type impurity concentrations. This may result in a switching lifetime that is temporarily much shorter than normally present in the structure of the semiconductor device. Consequently, one of the SET condition generating mechanisms may result from a particle striking the semiconductor device when a finite voltage is applied across it. As one skilled in the art will recognize, when the IN signal is in a complementary state, then the charge collection mechanism switches from the P-Channel transistor 302a to the N-Channel transistor 302b. 
Referring now to FIG. 3b, the NAND gate 304 may include a first P-Channel transistor 304a coupled in series with first and second N-Channel transistors 304b, 304c. The gates of the first P-Channel transistor 304a and the first N-Channel transistor 304b are configured to receive a first of two input signals (designated as an “IN1” signal) for which the NAND gate 304 performs the NAND logical function on. The NAND gate 304 provides an output signal on its output terminal (designated as an “OUT” node) 304e at a node at the intersection of the first P-Channel transistor 304a and second N-Channel transistor 304c. The NAND gate 304 also includes a second P-Channel transistor 304d having its drain coupled to the OUT node 304e. The gates of second N-Channel transistor 304c and the second P-Channel transistor 304d are configured to receive the second of two input signals (designated as an “IN2” signal).
If, for example, the IN1 signal is in a high state and the IN2 signal is in a low state, then (i) the first P-Channel transistor 304a and the second N-Channel transistor 304c are in OFF states, and (ii) the second P-Channel transistor 304d and the first N-Channel transistor 304b are in ON states, thereby causing the OUT signal to be in a high state.
A particle strike on the second N-Channel transistors 304c may create two different pull-down-current paths. The first-pull-down current path may occur from between the drain of and body tie of the second N-Channel transistor 304c. The second-pull-down-current path may occur from between the drain and source of the second N-Channel transistor 304c, if a parasitic BJT (not shown) is turned on. The first N-Channel transistor 304b, however, may present a blocking impedance in series with a pull-down current that can occur between the drain and source of the second N-Channel transistor 304c hindering its ability to pull the OUT signal to a low state.
If, for example, the IN1 and IN2 signals are in low states, then (i) the first and second N-Channel transistors 304b, 304c are in an OFF state, and (ii) the first and second P-Channel transistors 304a, 304d are in and ON state, thereby causing the OUT signal to be in a high state. As above, a particle strike on the second N-Channel transistor 304c creates two pull-down currents; one from between the drain to the body tie of the second N-Channel transistor 304c, and the second from between the drain to the source of the second N-Channel transistor 304c, if a parasitic BJT (not shown) is turned on. However, because the first N-Channel transistor 304b is in an OFF state, then the second pull-down current path may be cut off from VSS.
Thus, the only second pull-down current component of the OUT signal is the displacement current that results from charging the capacitance on node n1. This capacitance may be much smaller than the capacitance on the output node 304e, thereby causing little effect on the OUT signal. Accordingly, the majority of the current of the OUT signal results from the first-pull-down current.
The hole travel in the P-well of the second N-Channel transistor 304c, which can turn on its parasitic BJT, may also flow under the first N-Channel transistor 304b, and also turn on the parasitic BJT of the first N-Channel transistor 304b. Consequently, a pull-down current path from the output terminal through both the first and second N-Channel transistors 304c, 304b to VSS is created. Consequently, the state of the OUT signal may not be in the desired state.
As can be readily discerned from above, modern integrated circuits are susceptible to SEE conditions. Some solutions attempting to mitigate this susceptibility require the use of relatively complex combinational logic circuitry to provide logical or temporal isolation of SEE that would otherwise cause errors. These solutions typically are not area efficient. Further, logic and temporal isolation circuit solutions can affect overall circuit speed and may, in some cases, be applicable only to storage circuits. Moreover, the susceptibility of to SEE conditions is heightened by reduced feature sizes and higher clock speeds that are otherwise very desirable. Thus, an area-efficient solution that provides a high degree of SET, SEE and/or SEE hardness and that is also applicable to various circuit types (such as combinational logic circuits as well as memory circuits) is needed.